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n ec nec electronics inc. upd765a/UPD765B single/double density floppy-disk controller description features the upd765a/b is an lsi floppy disk controller (fdc) chip which contains the circuitry and control functions for interfacing a processor to 4 floppy disk drives. it is capableof either ibm 3740singledensity format (fm), or ibm system 34 double density format (mfm) including double-sided recording. the upd765a/b provides con- trol signals which simplify the design of an external phase-locked loop and write precompensation circuitry. the fdc simplifies and handles most of the burdens as- sociated with implementing a floppy disk interface. hand-shaking signals are provided in the upd765a/b which make dma operation easy to incorporate with the aid of an external dma controller chip, such as the upd8257. the fdc will operate in eitherthe dma or non- dma mode. in the non-dma mode the fdc generates interrupts to !he processor every time a data byte is to be transferred. in the dma mode, the processor need only load the command into the fdc and all data transfers occur under control of the fdc and dma controllers. there are 16 commands which the upd765a/UPD765B will execute. most of these commands require multiple 8-bit bytes to fully specify the operation which the processor wishes the fdc to perform. the following commands are available. read data read deleted data read id write data specify write id (format write) read diagnostic write deleted data scan equal seek scan high or equal recalibrate scan low or equal sense interrupt status version sense drive status. ordering information address mark detection circuitry is internal to the fdc which simplifies the phase-locked loop and read elec- tronics. the track stepping rate, head load time, and head unload time are user-programmable. the upd765a/UPD765B offers additional features such as multi-track and multi-side read and write commands and single and double density capabilities. fm, mfm control variable recording length: 128,256, .8192 bytes/ sector ibm-compatible format (single- and double- sided, single- and double-density) multi-sector and multi-track transfer capability drive up to 4 floppy or micro floppydisk drives data scan capability-will scan a single sector or an entire cylinder comparing byte-for-byte host memory and disk data data transfers in dma or non-dma mode parallel seek operations on up to four drives compatible with upd8080/85, upd8086/88, v-series and upd780 (z80@) microprocessors single-phase clock: 8 mhz maximum 3 +5v only z80 is a registered trademark of the zilog c orporation pin configuration device number upd765ac2 UPD765B package type 40-pin plastic dip 40-pin plastic dip max freq. of operation 8 mhz 8 mhz necel-000324 5-3
upd765a/UPD765B n ec pin identification no. symbol 1 reset 2 rd 3 wr 4 c s 5 a0 6-13 db0-db7 1 4 drq 1 5 dack 16 tc 17 index function reset input read control input write control input chip select input data or status select input bidirectional data bus dma request output dma acknowledge input terminal count input index input 18 int 19 clk 20 gnd 21 wclk 22 window 23 r data 24 sync 25 we 26 mfm 27 side 28 29 usn us1 interrupt request output clock input ground write clock input read data window input read data input vco sync output write enable output mfm output head select output fdd unit select output 30 wdata 31, 32 ps0 ps1 33 flt/trk0 34 wprt/2side 3 5 ready 36 hdld 37 fltr/step 38 lct/dir 39 m/seek 40 kc write data output preshift output fault/track zero input write protect/two side input ready input head load output fault reset/step output low current direction output read/write/ seek output dc power ( +5 v) pin functions reset (reset) int (interrupt) the reset input places the fdc in the idle state. it re- sets the output lines to the fdd to 0 (low), except pso, 1 and wdata (undefined), int and drq also go low; dbo-7 goes to an input state. it does not affect srt, hut, or hlt in the specify command. if the rdy input is held high during reset, the fdc will generate an inter- rupt within 1.024ms. to clear this interrupt, use the sense interrupt status command. the int output is fdc?s interrupt request. in non-dma mode, the signal is output for each byte. in dma mode, it is output at the termination of a command operation. clk (clock) clk is the input for the fdc?s single-phase, ltl-level squarewave clock: 8 mhz or 4 mhz. (requires a pull-up resistor.) rd (read strobe) the rd input allows the transfer of data from the fdc to the data bus when low and either c s or dack is asserted. wr (write strobe) the wr input allows the transfer of data to the fdc from the data bus when low. disabled when c s is high. a0 (data/status select) the a0 input selects the data register (a0 = 1) or status register (a0=o) contents to be accessed through the data bus. c s (chip select) the fdc is selected when c s is low, enabling r d and wr. dbo-db7 (data bus) dbo-db7 are a bidirectional 8-bit data bus. disabled when c s is high. drq (dma request) the fdc asserts the drq output high to request a dma transfer. dack (dma acknowledge) when the dack input is low, a dma cycle is active and the controller is performing a dma transfer. tc (terminal count) when thetc input is high, it indicates the termination of a dma transfer. it terminates data transfer during read/ write/scan commands in dma or interrupt mode. index (index) the index input goes high at the beginning of a disk track.
nec upd765a/UPD765B wclk (write clock) the wclk input sets the data write rate to the fdd. it is 500 khz for fm, 1 mhz for mfm drives, for 8 mhz opera- tion of the fdc; 250khz fm or 500 khz mfm for 4 mhz fdc operation. this signal must be input for read and write cycles wclk?s rising edge must be synchronized with clk?s rising edge, except for the UPD765B. window (read data window) the window input is generated by the phase-locked loop (pll). it is used to sample data from the fdd and in distinguishing between clock and data bits in the fdc. rdata (read data) the rdata input is the read data from the fdd, containing clock and data bits. to avoid a deadlock situation, input rdata and window together. wdata (write data) wdata is the serial clock and data output to the fdd. we (write enable) the we output enables write data into the fdd. sync (vco sync) the sync output inhibits the vco in the pll when low, enables it when high. mfm (mfm mode) the mfm output shows the vco?s operation mode. it is high for mfm, low for fm. side (head select) head 1 is selected when the side output is 1 (high), head 0 is selected when side is 0 (low). us0 us1 (unit select 0,1) the us0 and us1 outputs select up to 4 floppy disk drive units using an external decoder. ps0, ps1 (preshift 0,1) the ps0 and ps1 outputs are the write precompensation request signals for mfm mode. they determine early, late, and normal times for wdata shifting. ready (ready) the ready input indicates that the fdd is ready to re- ceive data. hdld (head load) the hdld output is the command which causes the read/write head in the fdd to contact the diskette. flt/trko (fault/track 0) in the read/write mode, the flt input detects fdd fault conditions. in the seek mode, trko indicates track 0 head position. wprt/2slde (write protect/two side) in the read/write mode, the wprt input senses write protected status (at the drive or media.) in the seek mode, 2 side senses two-sided media. fltr/step (fault reset/step) in the read/write mode, the fltr output resets the fault flip-flop in the fdd. in the seek mode, step outputs step pulses to move the head to another cylinder. a fault reset pulse is issued at the beginning or each read or write command prior to the hdld signal. lct/dlr (low current/direction) in the read/write mode, the lct output indicates that the r/w head is positioned at cylinder 42 or greater. in the seek mode, the dir output determines the direction the head will move in when it receives a step pulse. if dir is 0, seeks are performed in the outward direction; dir is 1, seeks are performed in the inward direction. rwlseek (read/write/seek) the rw/seek output specifies the read/write mode when low, and the seek mode when high. gnd (ground) ground. vcc(+5v) +5 v power supply. 5-5
upd765aiUPD765B n ec block diagram absolute maximum ratings ta = 250c power supply voltage, vcc -0 5 to +7v input voltage, v1 -0.5 to +7v output voltage, vo -0.510 +7v operating temperature, topt - 1ooc to +7ooc storage temperature, tstg -65c to +150c comment: exposing the device to stresses above those listed in the absolute maximum ratings could cause permanent damage. the device should not be operated under conditions outside the limits described in the operational sections of this specification. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. dc characteristics th= -1o?c to +70c,vcc = +5v%lo% __ limits teal parameter symbol min typ max unit conditions input voltage -0.5 v iow input voltage vih 2.0 5 v high output voltage 0.45 v low voltage 2.4 input voltage 0.5 low (clk + wclk) input voltage high (clk + wclk) supply current kc) kc v 0.65 v v 150 140 input load 10 current high input load -10 current low output leakage current high output leakage current low 10 -10 capacitance parameter input clock limits symbol min typ m a x unit 20 pf test conditions (note 1) input capacitance 10 pf (note 1) output cout 20 pf capacitance note: (1) all pinsexcept pin under test tied to ac ground. [note 1) 5-6
nec upd765a/UPD765B differences between ,upd765a and up d765b the UPD765B is a functionally enhanced version of the upd765a. differences are explained below. overrun bit [or] in upd765a, when executing a read- or write-type command (except read id and scan types), the result status or bit is not set if there is an overrun on the final byte of a sector. an improvement in the UPD765B allows it to set the or bit in any situation. drq reset when an overrun occurs, the upd765a needs dack input to reset drq. if dack is not available, an external dma controller continues to operate even after the fdc enters the r-phase (result phase), and stored result status may be transferred accidentally as ordinary data. on the other hand, the UPD765B resets drq auto- matically just before the r-phaseentry and independent of the dack input. see ac characteristics for drq reset timing. clock synchronization the UPD765B does not require synchronization between the clk and wclk inputs. version command the version command distinguishes the UPD765B from other devices. the st0 response to the version command is: part no. st0 value upd765a 80h UPD765B 90h 5-7
upd765aiupd7656 ac characteristics = -10 to = v parameter symbol min typ max unit conditions clock period 120 125 500 clk 240 250 ns clk parameter symbol min typ max conditions wclk cycle time 16 mfm = 0 8 mfm = 1 clock active (high, low) 40 wclk active time 250 350 ns note 4 clk wclk 0 ns delay only clock rise time 20 clock fall 20 ns wclk. rdata and 20 ns window time wclk, and 20 ns window fall time time -- dack 0 setup time to ro -- cs, dack 0 ns hold time from preshift time from wclk wclk delav 20 ns 20 100 ns width data access from 200 140 = 100 20 100 ns db to float delay 10 85 ns time from -- cs. oack aw 0 setup time to wr i rdata time 40 ns window cycle time 2 mfm=o oack 0 hold time ns 1 window hold time 15 n s from rdata width 200 ns data setup time to 100 ns window setup time to rdata 15 n s setup time 12 clk to seek notes 4, 5 seek setup time 7 to dir data hold time from 0 ns time from ns non-dma + mode + 135 direction setup time to step hold time from step t 5.0 int delay time from + 135 cycle time 13 ns (note 4) dack 140 ns delav drq dack 200 n s delay ns (note 4) dack width aa ns + 15 step active time 6 7 8 notes 4.5 (high) step cycle time 33 note 2note 2 fault reset 8.0 10 time (high) write data width hold time 15 clk after seek notes 3.4. 5 seek hold time 30 clk from dir notes 4, 5 dir hold time 24 after step index pulse 4 tc width reset width drq int 1 14 60 7 7 response time int dack ineffective only 1
ac characteristics (cont) parameter symbol min typ (1) max unit conditions delay from drq 800 ns s-mhz clk note 4 delay from drq 250 ns response time from drq 12 notes: (1) typical values for ta = 25c and nominal supply voltage. (2) under software controlthe range is from 1 ms to 16ms at 8-mhz clock period, and 2 ms to 32 ms at 4-mhz clock period. (3) when one device is executing a seek operation, sense drive status is executed on another device. (4) double these values for a 4-mhz clock period (5) thedrivesiderating has a variance of ~5ons from the minimum value. liming waveforms processor read operation processor write operation cs, dack
liming waveforms (cont) data input waveform for ac test (except clk, 2.4 0.45 clock (wclk, waveform for ac test output clock operation fdd write operation write enable 0 or write data 0 normal 0 0 0 early 0 invalid seek operation step overrun operation only) flj reset i fault reset fdd read operation 1 terminal count i reset i 5-10
n ec upd765a/UPD765B liming waveforms (cont) write clock index i index internal registers the upd765a/UPD765B contains two registers which may be accessed by the main system processor: a sta- tus register and a data register. the 8-bit main status register contains the status information of the fdc, and may be accessed at any time. the 8-bit data register (which actually consists of four registers, sto-st3, in a stack with only one register presented to the data bus at a time), stores data, commands, parameters, and fdd status information. data bytes are read out of, or written into, the data register in order to program or obtain the results after a particular command (table 3). only the status register may be read and used to facilitate the transfer of data between the processor and upd765a/ UPD765B. the relationship between the status/data registers and the signals rd, wr, and a0 is shown in table 1. table 1. status/data register addressing a0 rd wr function 00 1 read main status register 0 1 0 illegal 0 0 0 illegal 1 0 0 illegal 1 0 1 read from data register 11 0 write into data register the bits in the main status register are defined in table 2. table 2. main status register no. name function db0 d 0 b (fdd 0 busy) fdd number 0 is in the seek mode. ii any of the dnb bits is set fdc will not accept read or write command. db1 d1b (fdd 1 busy) fdd number1 is in the seek mode. if any of the dnb bits is set fdc will not accept read or write command. db2 d 2 b (fdd 2 busy) fdd number 2 is in the seek mode if any of the dnb bits is set fdc will not acceot db3 d 3 b read or write command (fdd 3 busy) fdd number 3 is in the seek mode. if any of the dnb bits is set fdc will not accept read or write command db4 cb a read or write command is in orocess. (fdc busy) fdc will not accept any other command. d b 5 exm this bit is set only during execution ohase (execution mode) in non-dma mode when db5 goes low, execution phase has ended and result phase has started. it operates only during non-dma mode of operation d b 6 dio indicates direction of data transfer be- (data input/output) tween fdc and data regrster if dio = 1, then transfer is from data register to the processor. if dio = 0, then transfer is from the processor to data register. d b 7 rqm indicates data register is ready to send or (request for master) receive data to or from the processor both bits dio and rqm should be used to per- form the hand-shaking functions of ?ready? and ?directron? to the processor the dio and rqm bits in the status register indicate when data is ready and in which direction data will be transferred on the data bus. see figure 1. figure 1. dio and rqm data in/out (dio) out fdc and into processor out processor and into fdc ii c 5-l 1
upd765a/UPD765B n ec table 3. status register identification pin no. name status register 0 d7, d6 ic (interrupt code) function d7=0 and d6=0 normal termination of command, (nt) command was completed and properly ex- ecuted d3 nr d7=0 and d6=1 abnormal termination of command, (at) execution of command was started but was not successfully completed. d7=1 and d6=0 invalid command issue, (ic) command which was issued was never started d65 d4 d7=1 and d6=1 abnormal termination because during command execution the ready srgnal from fdd changed state se when the fdc completes the seek com- (seek end) mand, this flag is set lo 1 (high). ec if a fault srgnal is received from the fdd, or (equipment check) if the track 0 srgnal fails to occur after 77 step pulses (recalibrate command) then this flag is set when the fdd is in the not-ready state and (not ready) a read or write command is issued, this flag is set if a read or write command is issued to side 1 of a single-sided drive, then this flag is set d2 hd this flag is used to indicate the state of the (head address) d1 us: (unit select 1) d0 us0 head at interrupt. this flag is used to indicate a drive unit number at interrupt. this flaa is used to indicate a drive unit (unit select 0) status register 1 d7 en (end of cylinder) number at interrupt when the fdc tries to access a sector be- yond the final sector of a cylinder, this flag is set not used. this bit is always 0 (low) de (data error) when the fdc detects a crc(1) error in ei- ther the id field or the data field, this flag is set d4 or (overrun) if the fdc is not serviced by the host sys- tem during data transfers within a certain time interval. this flaa is set. d3 not used. this bit is alwavs 0 (low). table 3. status register identification (cont) pin no. name status register 1 (cont) function d2 nd (no data) during execution of read data. read de- leted data write data. write deleted data or scan command, if the fdc cannot find the sector specified in the idr(2) register, this flag is set. d1 nw (not writeable) do ma (missing address mark) during execution of the read id command. if the fdc cannot read the id field without an error, then this flag is set. during execution of the read diagnostic command. if the starting sector cannot be found, then this flag is set. during execution of write data, write de- leted data or write id command. if the fdc detect: a write protect srgnal from the fdd. then this flag is set this bit is set if the fdc does not detect the idam before 2 index pulses it is also set if the fdc cannot find the dam or ddam af- ter the idam i s found. md bit of st2 is also status register 2 d7 ser at this time. not used. this bit is alwavs 0 (low) de cm (control mark) d5 dd during execution of the read data or scan command, if the fdc encounters a sector which contains a deleted data address mark, this flag is set also set if dam is found during read deleted data if the fdc detects a crc error in the data (data error in field then this flag is set da data field) wc (wrong cylinder) this bit is related to the nd bit, and when the contents of c(3) on the medium is dif- ferent from that stored in the idr. this flag is set d3 sh (scan equal hit) during execution of the scan command. if the condition of ?equal? is satisfied, this flag is set. d2 sn during execution of the scan command, if (scan not satisfied) the fd cannot find a sector on the cylin- der which meets the condition. then cthis flag is set d1 bc (bad cylinder) this bit is related to the nd bit. and when the contents of c on the medium is differ- ent from that stored in the idr and the con- tents of c is ffh. then this flag is set do md when data is read from the medium, if the (missing address fdc cannot find a data address mark or mark in data field) deleted data address mark, then this flag is set
upd765a/UPD765B nec table 3. status register identification (cont) command symbol description name a0 (address line 0) c (cylmder number) d (data) d7-d0 (data bus) dtl (data length) function a0 controls selection of main status register (a0=0) or data register (a0= 1). c stands for the current /selected cylinder (track) numbers 0 through 76 of the medium d stands for the data pattern which is going to be written into a sector during write id operation 8-bit data bus, where d7 stands for a most significant bit, and d0 stands for a least significant bit. when n is defined as 00. dtl stands for the data length which users are going to read out or write into the sector pin nc. name function status register 3 d7 ft this bit is used to indicate the status of the fault signal from the fdd. this bit is used to indicate the status of the (fault) d6 wp (write protec ted) write protected signal from the fdd. d56 ry this bit is used to indicate the status of the (ready) d4 to (track 0) 03 ts ready signal from the fdd. this bit is used to indicate the status of the track 0 signal from the fdd. this bit is used to indicate the status of the (two-side) d2 hd two-side signal from the fdd. this bit is used to indicate the status of the eot stands for the final sector number on a cylin- der durmg read or write operations, fdc will stop data transfer after a sector number equal to eot eot (end of track) (head address) d1 us1 (unit select 1) d0 us0 (unit select 0) note: side select signal to the fdd this bit is used to indicate the status of the unit select 1 signal to the fdd. this bit is used to indicate the status of the unit select 0 signal to the fdd. (1) crc = cyclic redundancy check (2) idr = internal data register (3) cylinder (c) is described more fully in the command symbol description. gpl (gap length) gpl stands for the length of gap 3. during read / write commands this value determines the num- ber of bytes that vco sync will stay low after two crc bytes during format command it deter- mines the size of gap 3 h stands for the logical head number 0 or 1. as specified in id field hd stands for a the physical head number 0 or 1 and controls the polarity of pin 27 (h = hd in all command words ) hlt stands for the head load time in the fdd (2 to 254 ms in 2 ms increments). hut stands for the head unload time after a read or write operation has occurred (16 to 240 ms in 16 ms increments) h (head address) hd (head) command sequence the upd765a/UPD765B is capable of performing 15 dif- ferent commands. each command is initiated by a multibyte transfer from the processor, and the result af- ter execution of the command may also be a multibyte transfer back to the processor. because of this multi- byte interchange of information between the upd765a/ UPD765B and the processor, it is convenient to consider each command as consisting of three phases: hlt (head load time) hut (head unload time) if mf is low, fm mode is selected, and if it is high, mfm mode is selected mf (fm or mfm mode) mt (multitrack) if mt is high, a multitrack operation is per- formed if mt = 1 after finishing read/write oper- ation on siude 0. fdc will automatically start searching for sector 1 on side 1 command phase: execution phase: result phase: the fdc receives all information re- quired to perform a particular opera- tion from the processor. the fdc performs the operation it was instructed to do. after completion of the operation, status and other housekeeping infor- mation are made available to the processor. n n stands for the number of data bvtes written in a (number) sector ncn ncn stands for a new cylinder number which is (new cylinder number) going to be reached as a result of the seek opera- tion; desired position of head nd nd stands for operation in the non-dma mode (non-dma mode) pcn pcn stands for the cylinder number at the (present cylinder number) completion of sense interrupt status command, position of head at present time table 4 shows the required preset parameters and results for each command. most commands require 9 command bytes and return 7 bytes during the result phase. the ?w? to the left of each byte indicates a com- mand phase byte to be written, and an ?r? indicates a result byte. the definitions of other abbriviations used in table are given in the command symbol description table. r [record) r/w (read/write) sc (sector) sk (skip) r stands for the sector number which will be read or written r/w stands for either read (r) or write (w) signal sc indicates the number of sectors per cylinder sk stands for skip deleted data address mark 5-13
upd765a/ UPD765B command symbol description (cont) command symbol description (cont) srt srt stands for the steooino rate for the fdd (1 to (step rate time) 16 ms in 1 ms increments). stepping rate applies to all drives (fh=1ms, eh=2ms, etc.). sto-st3 (status o-3) sto-st3 stands for one of four registers which store the status information after a command has been executed. this information is available dur- ing the result phase after command execution. these registers should not be confused with the main status register (selected by ao=o). sto-st3 may be read only after a command has been executed and contains information relevant to that particular command table 4. instruction set (notes 1,2) name function stp us0, us1 (unit select) during a scan operation if stp=1, the data in contiguous sectors is compared byte by byte with data sent from the processor (or dma); and if stp=2, then alternate sectorsare read and com- pared us stands for a selected drive number 0 or 3 phase read data command instruction code r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks w mt mf sk 0 0 1 10 command codes w x x x x x hd us1 us0 (note 3) w c sector id prior to command execution the 4 bytes w h are compared against header on floppy disk. w r w n w eot w gql w dtl execution result st0 st1 st2 c h data transfer between the fdd and main system status information after command execution sector id information after command execution rr r n read deleted data command w mt mf sk 0 1 1 0 0 command codes w x x x x x hd us, us0 w c sector id rnformation to command execution the 4 bytes w h are compared against header on floppy disk w r w n w eot w gpl w dtl execution data transfer between the fdd and main system result st0 st1 st2 c h status information after command execution sector id information after command execution r r rr n note: (1) symbols used in this table are described at the end of this section (2) a0 should equal 1 for all operations. (3) x = don?t care, usually made to equal 0.
n ec upd765a/UPD765B table 4. instruction set (notes 1,2) (cont) instruction code phase write data remarks command w mt mf 0 0 0 1 0 1 command codes w x x x x x hd w -c sector id information prior to command execution. the 4 h are compared against header on floppy wr w eot w gpl dtl st2 c h data transfer between the main system and fdd status after command execution sector id information after command execution r r n write deleted data command w mt mf 0 0 1 0 1 command codes w x x x x x hd us, w c sector information prior to the 4 bytes w are compared against header on floppy disk w r -p-----n- w eot w gpl w dtl execution data transfer between the fdd and main system result st1 status information after command execution st2 c h sector id information after command execution r n read diagnostic command w 0 mf sk 0 0 0 1 0 command codes w x x x x x hd w sector prior to command execution w h w r w w w n eot gpl w dtl data transfer between the fdd and main system fdc reads all data fields from index hole to edt. result st1 st2 c h n status information after command execution sector id information after command 5-15
table 4. set (notes instruction code remarks read command w0 mf 0 0 1 0 command codes w x x x x x hd us, executron the first correct id on the cylinder stored data register. status information after command execution st1 st2 c sector id read during executron phase from floppy h n id command w mf 1 1 1 command codes result w x x x x x hd us, w n bytes/sector wsc sectors/track w gpl gap3 w byte fdc formats an entire track. status information after command execution st1 st2 c in this case, the id has no h r- r n scan equal command w mt sk 1 0 0 0 1 command codes w x x x x x us, w c sector command execution w h w w w eot w gpl w stq execution data between the and main result st1 status after command execution st2 c h sector id information after command fl n note: (1) symbols used this table are described at the end of this section should equal 1 for all operations. (3) x don?t care, usually made to equal 0. 5-16
table 4. instruction set (notes code phase remarks scan or command mt mf sk 1 1 0 0 1 x x x x x hd us, c h n eot gpl stp command codes sector id to command data comoared between the fdd and result st1 st2 c r- r n status after command execution sector id information after command scan high equal command w mt mf sk 1 1 1 0 command codes w x x x x x us, w c sector id information prior to command execution w w w n w w w edt gpl stp execution result data compared between the fdd and system status information after command st1 st2 c sector id information after command h r- r command w o 0 0 d 11 command codes w x x x x x 0 head retracted to track 0 sense interrupt status command result w 0000 1 000 command codes status information about the fdc at the end of seek pcn specify command w 0 0 0 0 0 0 11 command codes w srt hut w hlt nd sense drive status command w 0 0 0 0 d 0 0 command codes w x x x x x hd us, result st3 status about fdd 5-17
table 4. instruction set (notes i, version command w x x x 1 0 0 0 0 command codes indicates 7658 indicates seek command w0000 1 11 1 command code w x x x x x hd us, w ncn execution head is positioned over proper cylinder on diskette invalid command w codes note: (1) symbols used in this table are described at the end of this section. (2) should equal 1 for all operations. (3) don?t care, usually made to equal 0. invalid command codes (no op- goes state) system configuration figure 2 shows an example of a system using a figure 2. system configuration 5-18
data format figure 3 shows the data transfer format for and in fm and mfm modes. figure 4 shows vco sync timing. figure 3. data format [fm mode] [mfm mode] figure 4. vco sync timing

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